Transistors in digital Integrated Circuit's (IC's) act as switches and can be turned on or turned off to create various logic functions. Typically, when the transistors are turned on they conduct their maximum current, when they have been turned off they conduct their minimum current, which is known as leakage current. When an IC is active, its logic consumes dynamic current related to switching node capacitances, and its inactive logic consumes leakage current. When an IC's logic is inactive it only consumes leakage current. As IC fabrication processes advance transistor sizes shrink, and smaller transistors generally have inherently larger leakage currents than larger transistors due to various effects of device physics. Leakage current is especially important for battery-powered devices that contain IC's since the leakage current will drain the battery even if the device isn't being used. For example, cell phones need to be recharged frequently even if they remain idle, due to the IC leakage currents draining the battery. If the IC leakage current in battery-powered devices such as cell phones can be reduced then battery life would be increased resulting in a better product.
Existing approaches for reducing IC leakage current generally increase design costs due to the use of specialized processes, libraries, larger macros, and/or additional CAD tools. Among some approaches discussed for use in the industry are: (A) Using a special non-standard, low leakage IC processes, which increases cost and greatly reduces design performance; (B) Using a special non-standard dual threshold IC process, which increases costs, provides the following 2 approaches: (1) Fast macros for circuit layout design based on low threshold (high leakage) transistors used for timing critical paths. Slow macros based on high threshold (low leakage) transistors used for slower paths. This approach requires additional CAD tools and a more complex design flow. (2) Use macros that contain high threshold (low leakage) transistors to gate off power in sleep mode, and fast low threshold (high leakage) transistors to be activated in operating mode. This approach results in larger library macros, which increase library macro area and design cost. (3) Dynamically vary VDD supply voltage, increase VDD for higher performance, and lower VDD to reduce performance and leakage current. This approach is unavailable as a standard design flow, requires complex analog controls, plus more extensive verification to validate performance at additional VDD levels. (4) Variable Threshold CMOS, uses back gate biasing to increase/lower effective threshold voltage of transistors. Raise threshold to reduce leakage, lower threshold to increase performance but with higher leakage. This approach requires a special triple well process to be very effective, and is unavailable within standard ASIC design flows, plus it increases die size due to distributing/connecting the back gate biasing signals. (5) Core based power gating used in custom IC's. This involves placing large power gating transistors between sections of digital logic and the power supply and/or ground supply within the IC's core area. These large transistors act as switches that turn can turn on or off access to the power supply. Removing access to the power supply greatly reduces the leakage current. These large transistors can restore power to the digital logic sections when they are in active mode.
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